Hi-Rel offers a variety of technical training courses at our facility for the new and experienced alike.
All classes require pre-payment or alternate arrangements to be agreed upon by Hi-Rel well ahead of the course presentation.
After 35 years teaching together, Howard Dicken and John Devaney are coming off the road. All of Hi-Rel’s training classes will now only be offered on site at Hi-Rel’s facility in Spokane.
Available Classes for 2018
|Hands-On Failure Analysis Workshop||August 13 – 17|
|Pre-Cap Visual Inspection Course||April 10 – 13|
|DPA (Destructive Physical Analysis) Seminar||March 5 – 9|
|Component Engineering 101||On Request|
|Failure Analysis/Failure Avoidance Seminar||On Request|
Hands-On Failure Analysis Workshop
This intensive 5 day, approximately 50-hour, lecture and lab builds on the lecture material covered in the 3 day Failure Analysis/Avoidance Seminar. The lab exercises cover “hands-on” curve tracing, liquid crystal hot spot detection, probing, plastic decapsulation, cross-sectioning, Scanning Electron Microscopy, and Energy Dispersive X-ray Analysis. Class size is limited to ensure that each student can participate in the lab work and operate the equipment. Texts provided for the class are: “Failure Analysis Techniques, Mechanisms and Photo Atlas” and “Physics of Semiconductor Failures.”
Fee: $3500 per student. Contact Chelsey Garrison for availability.
Pre-Cap Visual Inspection Course
This course is intended as a refresher and certification for line inspectors. It covers the basics of semiconductor manufacturing to establish the vocabulary used in the specifications. The specifications covered are MIL-STD 750 method 2072, “Visual Inspection of Transistors,” MIL-STD 883, method 2010, “Visual Inspection of Integrated Circuits,” and MIL-STD method 2017, “Visual Inspection of Hybrids.” This is an intensive three and a half days of lecture and a final written and visual examination. The course materials are Hi-Rel’s technology modules and color illustrated-annotated specification which translates each line of criteria into a detailed drawing of good and bad.
Fee: $2500 per student, minimum 5 students. Contact Chelsey Garrison for availability.
DPA (Destructive Physical Analysis) Seminar
This course is a comprehensive 5-day lecture and lab combination presented for the purpose of training DPA Engineers, Technicians, and Component Engineers in the history / background, physics, methodology, and techniques involved in the performance of DPA Testing or Review Processes. The class will cover all part types widely used in current Space programs: Microcircuits, Hybrids, Transistors, Diodes, Capacitors, Resistors, Connectors, Magnetics, Crystals, Relays, and Fuses. The tests to be covered will be: External Visual Inspection, External Prohibited Materials Analysis (PMA), Hermeticity Testing, Real Time Radiography, Solderability Testing, PIND, IGA (RGA), Terminal Strength Testing, Delidding or Decapsulation Techniques, Internal Visual Inspection, Cross Sectioning, Internal PMA Testing, Bond Pull Testing, Glassivation Removal for SEM Metallization Inspection, SEM Metallization Step Coverage Inspection, and Die Shear Testing. Students will leave the course with a working knowledge of MIL-STD-1580, as well as the MIL-STD-883, 750 and 202 Tests that apply to DPA.
Fee: $3500 per student, minimum 2 students. Contact Chelsey Garrison for availability.
Component Engineering 101
This three day interactive seminar is designed to acquaint the attendees with what was historically required of the component engineer. Today, many component engineers in the industry only work with the paper specifications and have never looked inside of the device they’re specifying! This seminar is designed to show the attendees the need to know the component technology, how the part is made, and the potential failure mechanisms associated with the device so that the best selection can be made. Screen and Burn-in testing will also be examined with the rationale for each of the tests and what to do with the results. Examples covered will include integrated circuits, both bipolar and CMOS, transistors, diodes, power MOSFETs, capacitors, and resistors. Just one item covered in this seminar could help your company avoid a million dollar design mistake.
(Scheduled on demand.)
Fee: $2000 per student, minimum 5 students. Contact Chelsey Garrison for availability.
Failure Analysis/Failure Avoidance Seminar
A 3 day lecture course scheduled on demand at our Spokane facility or yours. This is a lecture class which includes a basic introduction Semiconductor Theory, Manufacturing and Layout coupled with Failure Mechanisms, Failure Analysis Techniques and Methodology and Instrumentation. The content emphasis can be varied as desired. It has been used as a basic introductory tool for new failure analysis and component engineers and as a refresher class for people who have been out of touch for a while. Class size is unlimited but experience shows that 20 to 25 is about the maximum effective size. Texts for the class are: “Failure Analysis Techniques, Mechanisms and Photo Atlas” and “Physics of Semiconductor Failures.”
(Scheduled on demand.)
Fee: Quoted on request, minimum 10 students. Contact Chelsey Garrison for availability.
Hi-Rel reserves the right to cancel due to unforeseen circumstances.