Hi-Rel offers a variety of technical training courses at our facility, and when possible, can present instruction at your facility. All classes require pre-payment or alternate arrengments to be agreed upon by Hi-Rel well ahead of the course presentation.
Hands-On Failure Analysis Workshop
This intensive 5 day, approximately 50-hour, lecture and lab builds on the lecture material covered in the 3 day Failure Analysis/Avoidance Seminar. The lab exercises cover "hands-on" curve tracing, liquid crystal hot spot detection, probing, plastic decapsulation, cross-sectioning, Scanning Electron Microscopy, and Energy Dispersive X-ray Analysis. Class size is limited to ensure that each student can participate in the lab work and operate the equipment. Texts provided for the class are: "Failure Analysis Techniques, Mechanisms and Photo Atlas" and "Physics of Semiconductor Failures."
Dates for 2010: February 22 - 26, May 3 - 7, August 16 - 18 and October 11 - 15.
Fee: $3000 per student. Contact Kristy White for availability.
Pre-Cap Visual Inspection Course
Intended as a refresher and certification course for line
inspectors. It covers the basics of semiconductor manufacturing to
establish the vocabulary used in the specifications. The specifications
covered are MIL-STD 750 method 2072, "Visual Inspection of Transistors,"
MIL-STD 883, method 2010, "Visual Inspection of Integrated
Circuits," and MIL-STD method 2017, "Visual Inspection of Hybrids."
This is an intensive three and one half days of lecture and a final
written and visual examination. The text is Hi-Rel's color
illustrated-annotated specification and technology modules
(on CD-ROM) which translates each line of criteria into a detailed
drawing of good and bad examples.
Dates for 2010: April 20 - 23.
Fee: $2000 per student. Contact Kristy White for availability.
Component Engineering 101
This three day interactive seminar is designed to acquaint the attendees with what was historically required of the component engineer. Today, many component engineers in the industry only work with the paper specifications and have never looked inside of the device they're specifying! This seminar is designed to show the attendees the need to know the component technology, how the part is made, and the potential failure mechanisms associated with the device so that the best selection can be made. Screen and Burn-in testing will also be examined with the rationale for each of the tests and what to do with the results. Examples covered will include integrated circuits, both bipolar and CMOS, transistors, diodes, power MOSFETs, capacitors, and resistors. Just one item covered in this seminar could help your company avoid a million dollar design mistake. Minimum 5 students.
Dates for 2010: July 20 - 22. (Off-site training available on demand.)
Fee: $1800 per student, minimum 5 students. Contact Kristy White for availability.
SEM (Scanning Electron Microscopy) Seminar
A 3 day lecture and lab in which each phase of the
lecture material is followed by a lab demonstration and the student
then performs the same exercises on the SEM. The lectures cover that
material which the student needs to understand to "get the most" out of
his/her SEM for Failure Analysis, primarily semiconductors. For this
reason, sessions on Voltage Contrast and Electron Beam Induced Current
(EBIC) are included. A half day is devoted to the basics of X-ray
Spectroscopy. Maximum of four attendees to ensure adequate instrument
time for each student. Text for the class is "Microanalysis-Scanning
Electron Microscopy" by Meny and Tixer.
Dates for 2010: (Scheduled on demand.)
Fee: $3000 per student, minimum 2 students. Contact Kristy White for availability.
Failure Analysis/Failure Avoidance Seminar
A 3 day lecture course scheduled on demand at our Spokane
facility or yours. This is a lecture class which includes a basic
introduction Semiconductor Theory, Manufacturing and Layout coupled
with Failure Mechanisms, Failure Analysis Techniques and Methodology
and Instrumentation. The content emphasis can be varied as desired. It
has been used as a basic introductory tool for new failure analysis and
component engineers and as a refresher class for people who have been
out of touch for a while. Class size is unlimited but experience shows
that 20 to 25 is about the maximum effective size. Texts for the class
are: "Failure Analysis Techniques, Mechanisms and Photo Atlas" and
"Physics of Semiconductor Failures."
Dates for 2010: (Scheduled on demand.)
Fee: Quoted on request, minimum 10 students. Contact Kristy White for availability.